1. Field
The embodiments discussed herein are directed to a transmitter/receiver device, such as a SERDES (serializer/deserializer), including a transmitter unit which converts a parallel signal to a serial signal to transmit the serial signal and a receiver unit which receives a serial signal to convert the serial signal to a parallel signal, and it relates to a method of testing the same.
2. Description of the Related Art
In recent years, in a telecommunications technology, serialization of transmission signals and an increase in speed thereof have been progressing in accordance with an increase in telecommunication capacity. A backbone communication device with back plane (BP) transmission of 3.125 Gbps per signal line, such as 10-gigabit Ethernet (IEEE802.3ae), has been realized. Further, ultra-high-speed transmission of 6.5 Gbps and 10 Gbps per signal line is under development as next-generation technology.
FIG. 1 shows an overview of the back plane transmission. In a line card 10A (10B), a low-speed parallel signal is converted to a high-speed serial signal by a serializer 30A (30B) of a SERDES 20A (20B). Then, the high-speed serial signal is supplied to the line card 10B (10A) via the connector 40B (40A) after transmitted in a back plane 50 via a connector 40A (40B). Thereafter, in the line card 10B (10A), the high-speed serial signal supplied via the connector 40B (40A) is converted to a low-speed parallel signal by a deserializer 40B (40A) of the SERDES 20B (20A).
In a case where a high-frequency signal such as this high-speed serial signal is transmitted through a transmission medium such as a cable or a back plane, amplitude attenuation of the signal becomes larger and a change amount of its phase also increases in proportion to the frequency and transmission distance. The amplitude attenuation of the signal narrows an opening width in a vertical direction of an eye at a receiving end, and the change of the phase causes ISI (Inter Symbol Interference) to occur. If the inter symbol interference occurs, timing jitter occurs to narrow an opening width in a horizontal direction of an eye at the receiving end. As a result, the eye opening width of a signal waveform at the receiving end is narrowed as shown in FIG. 1, which makes it difficult to receive the signal. In this manner, in the transmission of the high-speed serial signal, the transmission distance is limited to a larger extent as the frequency becomes higher. Therefore, in order to realize quality improvement of a communication apparatus, it is very important, in designing the communication apparatus, to select/employ a SERDES with the knowledge of a transmittable distance of a signal.
The SERDES has a pre-emphasis function as one of its internal functions. The pre-emphasis function is to find a frequency characteristic (loss characteristic) of a transmission medium in advance and emphasize a high-frequency component of a transmission signal in order to compensate the characteristic, thereby widening an eye opening width at a receiving end. FIG. 2 shows a configuration example of a pre-emphasis circuit (4-tap pre-emphasis circuit). FIG. 3 shows an operation example of the pre-emphasis circuit in FIG. 2. In a pre-emphasis circuit 100, the following operations are executed by a delay circuit 102 and an output circuit 103 under the control of a control circuit 101. In the delay circuit 102, a serial signal IN is divided into four signals S1˜S4 which are shifted from one another by 1 UI (Unit Interval) (FIG. 3(a)). Thereafter, in the output circuit 103, the signals S1˜S4 are added, with output amplitudes thereof being adjusted by a DAC (Digital to Analog Converter), a differential amplifier, or the like. Consequently, at change points from “0” to “1” and change points from “1” to “0” in a serial signal OUT, a high-frequency component is emphasized (FIG. 3(b)). A 5-tap pre-emphasis circuit is disclosed in “Ultra-High-Speed CMOS Interface Technology”, Journal FUJITSU, November, 2004, written by Kotaro Goto et al.
Another internal function of the SERDES is an equalizing function. The equalizing function is to find a frequency characteristic of a transmission medium in advance and emphasize a high-frequency component of a transmission signal in order to compensate the characteristic, thereby widening an eye opening width at a receiver side. FIG. 4 shows a configuration example of an equalizing circuit. FIG. 5 shows an example of frequency characteristics in an essential part of the equalizing circuit in FIG. 4. An equalizing circuit 200 includes a main circuit 201 and a control circuit 202. The main circuit 201 includes: a path P11 for transmitting a low-frequency component (DC component) of a serial signal INP; a path P12 for amplifying a high-frequency component of the serial signal INP; a path P21 for transmitting a low-frequency component of a serial signal INN; and a path P22 for amplifying a high-frequency component of the serial signal INN. Each of the paths P11, P12, P21, P22 is constituted by a filter, an amplifier, and so on. According to the frequency characteristics as expressed by the characteristic curves CVa, CVb shown in FIG. 5, the control circuit 202 controls characteristics of the filters and gains of the amplifiers in the paths P12, P22 of the main circuit 201.
A capacitor element C1 is connected between a signal line of the serial signal INP and the path P12, and a resistor element R1 is connected between a connection node of the capacitor element C1 and the path P12 and a voltage line of a voltage VTT. Similarly, a capacitor element C2 is connected between a signal line of the serial signal INN and the path P22, and a resistor element R2 is connected between a connection node of the capacitor element C2 and the path P22 and the voltage line of the voltage VTT. Further, signals having passed through the paths P11, P12 are synthesized and the resultant signal is supplied to a buffer B1, and signals having passed through the paths P21, P22 are synthesized and the resultant signal is supplied to a buffer B2. Then, a comparator CMP generates serial signals OUTP, OUTN from output signals of the buffers B1, B2. In the equalizing circuit 200 as configured above, the frequency characteristic of the path P12 (P22) of the main circuit 201 is controlled by the control circuit 202, and the signals having passed through the paths P11, P12 (P21, P22) are synthesized in the main circuit 201, so that the serial signal OUTP (OUTN) with a wide eye opening width is generated even when an eye opening width of the serial signal INP (INN) is narrowed due to the signal transmission.
FIG. 6 shows a back plane transmission margin test of a SERDES in a prior art. The back plane transmission margin test is conducted by using a SERDES 1 as a test target and a pseudo back plane 5. The SERDES 1 includes a transmitter unit 2, a receiver unit 3, and a control unit 4. The transmitter unit 2 includes a pattern generator 2a, a selector 2b, a PLL (Phase-Locked Loop) circuit 2c, a serializer 2d, a pre-emphasis circuit 2e, and a driver 2f. 
The pattern generator 2a generates a pseudo random pattern such as a PRBS (Pseudo Random Bit Stream) signal to output it to the selector 2b in response to a command from the control unit 4. According to a command from the control unit 4, the selector 2b selects a parallel signal PDI supplied via an external pin P1 or the parallel signal supplied from the pattern generator 2a to output the selected signal to the serialize 2d. The PLL circuit 2c generates a multiplied clock based on a reference clock CKR supplied via an external pin P2, to output the multiplied clock to the serializer 2d. 
The serializer 2d converts the parallel signal supplied from the selector 2b to a serial signal synchronous with the clock supplied from the PLL circuit 2c to output the serial signal to the pre-emphasis circuit 2e. According to a command from the control unit 4, the pre-emphasis circuit 2e applies a pre-emphasis process (process to emphasize a high-frequency component) to the serial signal supplied from the serializer 2d to output the resultant serial signal to the driver 2f. The driver 2f outputs differential serial signals SDOP, SDON corresponding to the serial signal supplied from the pre-emphasis circuit 2e, to an external part via external pins P3, P4.
The receiver unit 3 includes a receiver 3a, a CDR (Clock and Data Recovery) circuit 3b, a deserializer 3c, and an error detector 3d. The receiver 3a outputs to the CDR circuit 3b a serial signal corresponding to differential serial signals SDIP, SDIN supplied via external pins P6, P7. The CDR circuit 3b recovers a clock and data regarding the serial signal supplied from the receiver 3a to output the serial signal to the deserializer 3c. 
The deserializer 3c converts the serial signal supplied from the CDR circuit 3b to a parallel signal to output the resultant signal as a parallel signal PDO to an external part via an external pin P8. The deserializer 3c also outputs the parallel signal PDO to the error detector 3d. In response to a command from the control unit 4, the error detector 3d detects a BER (Bit Error Rate) of the parallel signal supplied from the deserializer 3c. The control unit 4 controls the circuits of the transmitter unit 2 and the circuits of the receiver unit 3 according to a control signal CTL supplied via an external pin P5.
The back plane transmission margin test of the SERDES 1 as configured above is conducted in the following manner. First, the pattern generator 2a generates a pseudo random pattern to supply the pseudo random pattern as a low-speed parallel signal to the serializer 2d via the selector 2b. Next, the serializer 2d converts the low-speed parallel signal supplied form the selector 2b to a high-speed serial signal synchronous with a high-speed clock supplied from the PLL circuit 2c. Then, the pre-emphasis circuit 2e performs the pre-emphasis process to the serial signal supplied from the serializer 2d and thereafter outputs the resultant serial signal to an external part (pseudo back plane 5) via the driver 2f and the external pins P3, P4. The differential serial signals SDOP, SDON outputted from the external pins P3, P4 of the SERDES 1 are transmitted through the pseudo back plane 5, and are thereafter supplied as the differential serial signals SDIP, SDIN to the external pins P6, P7 of the SERDES 1.
A clock and data of the high-speed serial signal (serial signal corresponding to the differential serial signals SDIP, SDIN) supplied from the receiver 3a are recovered by the CDR circuit 3b, and thereafter, the high-speed serial signal is converted to a low-speed parallel signal by the deserializer 3c. Then, the error detector 3d detects a bit error rate of the low-speed parallel signal supplied from the deserializer 3c. At this time, a plurality of the pseudo back planes 5 different in transmission distance (transmission loss) are used and the maximum transmission distance when the bit error rate detected by the error detector 3d is a predetermined value (for example, 10 to the power of −12) or lower is measured.
As for jitter tolerance, jitter amounts at output far ends of transmission signals (that is, jitter amounts of the transmission signals when they are inputted to SERDES) are specifically defined in the XAUI (10 Gigabit Attachment Unit Interface) standard for 10 gigabit Ethernet prescribed in, for example, IEEE802.3ae, and a device compliant with the XAUI standard is required to be capable of receiving a transmission signal on which jitter of TJ (Total Jitter)=0.65 UI or more is superimposed.
FIG. 7 shows a jitter tolerance test of a SERDES in a prior art. The jitter tolerance test is conducted by using a SERDES 1 as a test target, a BERT (Bit Error Tester) 6, a sinusoidal generator 7, and a pseudo back plane 8. The BERT 6 includes an error detector 6a, a signal generator 6b, and a pattern generator 6c. 
In the jitter tolerance test, a PRBS pattern (serial signal) is outputted from the pattern generator 6c of the BERT 6. At this time, the sinusoidal generator 7 phase-modulates a sinusoidal signal of 100 kHz˜80 MHz to apply sinusoidal jitter to a reference clock of the signal generator 6b of the BERT 6. Consequently, the pattern generator 6c of the BERT 6 outputs a high-speed serial signal on which the SJ (Sinusoidal Jitter) is superimposed. The serial signal with the jitter superimposed thereon is inputted to external pins P6, P7 of the SERDES 1 and the error detector 3d detects a bit error rate. At this time, the maximum jitter amount receivable by the SERDES 1 is measured while an amount of the jitter in the high-speed serial signal is varied. This characteristic is called Sinusoidal Jitter Tolerance, which is defined as a mask in the standard such as the SONET (Synchronous Optical Network) standard, the XAUI standard, and the like. Further, the XAUI standard specifically defines jitter components regarding the jitter tolerance, and conditions set therein are TJ=0.65 UI, DJ=0.37 UI, DJ+RJ=0.55 UI. Therefore, in some cases, when the jitter tolerance test is conducted, the pseudo back plane 8 is provided between the BERT 6 and the SERDES 1 to superimpose DJ (Deterministic jitter) due to inter symbol interference on the differential serial signals SDIP, SDIN inputted to the external pins P6, P7 of the SERDES 1. In this manner, to test a device compliant with the XAUI standard and the like, some mechanism capable of adjusting an amount of superimposed jitter of each jitter component is required.
As a technique aiming at an efficient jitter tolerance test, well-known is a technique to conduct a jitter tolerance test by inputting an output signal of a transmitter unit of a SERDES to a receiver unit via an external unit and delaying the output signal in the external unit to give arbitrary waveform deterioration to the output signal (see, for example, Japanese Unexamined Patent Application Publication No. 2004-340940).
In the back plane transmission margin test shown in FIG. 6, in order to reproduce waveform deterioration due to the back plane transmission of the differential serial signals SDOP, SDON outputted from the SERDES 1 (increase in jitter due to the amplitude attenuation of the signal and inter symbol interface), it is necessary to use the plural pseudo back planes 5 different in wiring length (transmission distance). However, fabricating the plural pseudo back plane 5 different in wiring length costs extremely high.
Further, in the jitter tolerance test shown in FIG. 7, in order to superimpose desired jitter on the differential serial signals SDIP, SDIN inputted to the SERDES 1, a very expensive testing apparatus such as the BERT 6 has to be used, and a testing apparatus compatible to 10 Gbps signal transmission sometimes costs several million yen, which has made it difficult in terms of cost for a user to conduct the test.